Skip to content

Fixed RISCV T-Head 1520 CPU identification#141

Merged
fenrus75 merged 1 commit intofenrus75:masterfrom
renat-sabitov:t-head-1520-lpi4a
Nov 2, 2023
Merged

Fixed RISCV T-Head 1520 CPU identification#141
fenrus75 merged 1 commit intofenrus75:masterfrom
renat-sabitov:t-head-1520-lpi4a

Conversation

@renat-sabitov
Copy link

@renat-sabitov renat-sabitov commented Nov 2, 2023

T-Head 1520 is a RISCV CPU. I suggest using isa line to mark the end of processing.

sipeed@lpi4a:~$ cat /proc/cpuinfo 
processor	: 0
hart		: 0
isa		: rv64imafdcvsu
mmu		: sv39
cpu-freq	: 1.848Ghz
cpu-icache	: 64KB
cpu-dcache	: 64KB
cpu-l2cache	: 1MB
cpu-tlb		: 1024 4-ways
cpu-cacheline	: 64Bytes
cpu-vector	: 0.7.1

processor	: 1
hart		: 1
isa		: rv64imafdcvsu
mmu		: sv39
cpu-freq	: 1.848Ghz
cpu-icache	: 64KB
cpu-dcache	: 64KB
cpu-l2cache	: 1MB
cpu-tlb		: 1024 4-ways
cpu-cacheline	: 64Bytes
cpu-vector	: 0.7.1

processor	: 2
hart		: 2
isa		: rv64imafdcvsu
mmu		: sv39
cpu-freq	: 1.848Ghz
cpu-icache	: 64KB
cpu-dcache	: 64KB
cpu-l2cache	: 1MB
cpu-tlb		: 1024 4-ways
cpu-cacheline	: 64Bytes
cpu-vector	: 0.7.1

processor	: 3
hart		: 3
isa		: rv64imafdcvsu
mmu		: sv39
cpu-freq	: 1.848Ghz
cpu-icache	: 64KB
cpu-dcache	: 64KB
cpu-l2cache	: 1MB
cpu-tlb		: 1024 4-ways
cpu-cacheline	: 64Bytes
cpu-vector	: 0.7.1

Also, topology doesn't have information for core_id

$ cat /sys/devices/system/cpu/cpu*/topology/core_id
-1
-1
-1
-1

@renat-sabitov
Copy link
Author

renat-sabitov commented Nov 2, 2023 •
edited
Loading

It's different to #125, but should support VisionFive 2 board as well

@fenrus75
Copy link
Owner

fenrus75 commented Nov 2, 2023

Patch looks sensible so I'm about to hit the "merge" button.
Thank you for your contribution!

@fenrus75 fenrus75 merged commit 4bdfba1 into fenrus75:master Nov 2, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

@fenrus75 fenrus75 fenrus75 approved these changes

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

3 participants

@renat-sabitov @fenrus75 @rsabitov